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Senior FPGA oder ASIC Digital Design Engineer (m/w/x)

65.000 € - 80.000 € annual
Dresden (hybrid)
Senior
Flexible working hours
30 Vacation days
🇩🇪 B1/B2
🇬🇧 C1

Please apply here on „MINTbund.de“ with the „Apply Now“ link/button at the top right.

Note: Please apply exclusively via our direct application link hosted by Empfehlungsbund and MINTbund.de: https://www.mintbund.de/jobs/276784/senior-fpga-oder-asic-digital-design-engineer-m-strich-w-strich-x-in-dresden?locale=en. We are looking forward to meet you!

Your tasks:

  • Participation in the definition of our system-on-chip architecture
  • Responsibility for the RTL design of the digital blocks and their integration at system level
  • Development and verification of our wireless system-on-chip solution
  • Support and implementation of functional verification at chip and block level
  • Support with product qualification, testing and ramp-up
  • Documentation during development
  • Working in an international team (good English skills are required)

Your profile:

  • Bachelor's degree in electrical engineering/electronics or comparable
  • Good knowledge of ASIC/FPGA SoC architecture, digital design and verification
  • Programming languages: SystemVerilog, Verilog, VHDL
  • Experience in the development of verification methods and infrastructures for automated testbenches
  • Advantageous:
    • Experience in synthesis for various target technologies

We offer:

  • Permanent position with a high level of personal responsibility and very good development opportunities
  • Work in an international, friendly and motivated team that will be happy to support you with any questions you may have
  • Flat hierarchies, openness to change and appreciation of your ideas
  • An appreciative corporate culture characterized by a high degree of team spirit and trust, regular team events
  • Flexible working hours (flexitime) with 1 regular home office day per week, further opportunities for mobile working by arrangement
  • Attractive benefits: free job or Germany ticket or job bike (monthly flat rate of €55) + free use of the gym in the building
  • Bright and comfortable offices in a central Dresden location (Plauen)
  • Fast and uncomplicated application process
DeutschEnglish
DECT, NR+, 5G, IoT, Mikrocontroller, Microcontroller, Hardware, smart, Startup, Elektrotechnik, MINTbund.de, Empfehlungsbund

This Job resp. positions as 'Senior FPGA oder ASIC Digital Design Engineer (m/w/x)' is vacant in following addresses: 01187 Dresden in Sachsen.

Short profile of Last Mile Semiconductor GmbH

Based in Dresden, Germany – the heart of Silicon Saxony – we are a semiconductor startup for the breakthrough development of a new non-cellular 5G wireless chipset that enables secure massive IoT use cases.

Driven by a vision of a future where technology is seamlessly integrated into our daily lives, encompassing homes, industries, public spaces and healthcare, we strive to optimize resource and energy consumption while establishing global digital sovereignty. To realize this vision, we are actively developing a low-cost and ultra-low-power 5G wireless chipset based on the revolutionary NR+ non cellular private 5G standard.

We are a member of the community because we want to offer all talented specialists the opportunity to advance the Dresden location with their know-how, even if we are unable to offer a position ourselves.

Ms. Jessica Hinkelmann

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